Ashish Sharma

About Ashish Sharma

Lead ASIC Design Verification Engineer | PCIe | AXI | SystemVerilog | UVMWith over 7.5 years of hands-on experience in ASIC Design Verification, I specialize in building robust, scalable testbenches and driving verification strategies from the ground up. Currently leading IP verification projects at Intel (via Wipro Ltd), I have a proven track record of delivering high-quality results across multiple domains including PCIe Gen 1–5, AXI, DMA, and register validation.My work has spanned on-site collaborations, cross-functional stakeholder discussions, customer-facing roles, and mentoring junior engineers. I’ve been recognized for excellence with awards such as “Beyond The Call of Duty” and “Inspiring Performance” — reflecting my commitment to quality, ownership, and innovation in verification. Core Expertise:• Protocols: PCIe (1/2/3/4/5), AXI, DMA• Tools & Languages: SystemVerilog, UVM, VCS, Verdi, DVE, Perl• Activities: VIP Integration, RAL Model Testing, Scoreboard Logic, Debugging, GLS, Coverage Closure• Leadership: Team handling, project planning, stakeholder communicationLet’s connect if you’re passionate about verification, looking to collaborate, or exploring ideas around high-performance IPs and SoC design.

Experience

1. Vlsi Technical Lead

   Wipro

   Jan 2024 — Present · Pune, IN

   PSG DMA IP Verification (Altera Account): July 2024 - Dec 2025Led end-to-end verification ownership of DMA IP, managing a 6-member verification team and drivingexecution from planning to coverage sign-off.Migrated a highly directed testbench to a constrained-random methodology, identifying criticalrandomization knobs and constraints to improve corner-case scenarios.Verified complex PCIe features including out-of-order transactions, RCB handling, and MPS/MRRSconfiguration.Owned AXI-4 and AXI-ST verification, covering 4K boundary crossing, large transfer scenarios, and error propagation, contributing to both stimulus and testbench enhancements.Designed and integrated feature-aware scoreboard checkers to handle data integrity verification.Achieved functional coverage beyond 90% by leading coverage reviews with designers, identifying genuine gaps, and applying justified waivers for unsupported scenarios.MGV PCC IP Verification (Intel Account): Jan 2024 - June 2024Led IP-level verification from scratch, owning test plan creation, testbench development, and execution,while managing a team of two verification engineers.Integrated AXI VIP to generate traffic scenarios at the PCC ingress interface, enabling early detection ofprotocol and datapath issues.Collaborated closely with designers to understand datapath behavior and CSR architecture. ImplementedUVM RAL model for CSR access.Served as the technical point of contact for customers, delivering regular status updates, leading technical reviews, and driving resolution of critical debugs.