Ashish Mehta
Sr Principal Design Engineer at Cadence Design Systems
- Role
- Sr Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Sr Principal Design Engineer
Jul 2019 — Present
Education
Savitribai Phule Pune University
Master of Engineering - MEng, VLSI and Embedded System
2013 — 2015
Skills
- Very-Large-Scale Integration (Vlsi)
- Soc
- Timing Closure
- Asic
- Rtl Coding
- Ncsim
- Verilog
- Dft
- Debugging
- Static Timing Analysis
- Systemverilog
- Integrated Circuits (Ic)
- Amba Ahb
- Low-Power Design
- Formal Verification
- Vlsi
- Rtl Design
- Functional Verification
- Ic
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