Ashish Kumar Sharma

About Ashish Kumar Sharma

Currently working as a SoC Power Optimization engineer at Qualcomm India Private Limited, Hyderabad.Masters in Electronics Engineering with Specialization in Electronic Circuits & systems design from Aligarh Muslim University.My technical skills includes-Course Studied – UPF Power aware design and verification, Digital System Design, Analog IC Design, Current Mode Circuits & Systems, RF Circuits & Systems, Nano Electronic Device, Very Large Scale Integration (VLSI)Analog Front End – Systematic Design of Inverter, Single Stage Amplifier, Difference amplifier, 5 Transistor Based OTA, Level shifters, Sample & Hold, Dynamic Comparator, RC Delay Unit with real input & Output Environment, High Speed Flip flop Design etc.Analog Back End – Layout of Inverter, Single stage amplifier, Difference Amplifier, XOR GATE, 3 Input NAND & NOR GATE etc.Digital Design – Design of Digital circuit (Full adder, Ripple carry adder, Frequency divided by 3 Circuit, Register, Sequence detector) on Xilinx Vivado Tool. TOOL - Cadence virtuoso, Xilinx Vivado, Hspice Tool, Pspice Tool, LTspice.Technology Used – 20nm Double Gate TFET for TFET Level shifter Design, 45nm & 90nm for Analog Circuits Design, 180nm For Both Circuit Design & Layout, 16nm High Performance PTM Model For RC Delay unit with real input & Output Environment and High speed flip flop design.Language Known – VerilogMaster\'s Project on \"TFET Based Voltage level shifter Design\" Status - CompletedReached through this profile or my email a••••••••@gmail.com or my Mob No - 76••••••10

Experience

1. Engineer

   Qualcomm

   Oct 2021 — Present · Hyderabad, IN

   Currently working as an SoC Power optimization engineer

Education

• AJAY KUMAR GARG ENGINEERING COLLEGE, GHAZIABAD

  B.TECH, ELECTRONICS & INSTRUMENTATIOPN

  2015 — 2019

• Aligarh Muslim University

  M.TECH, ELECTRONIC CIRCUITS & SYSTEMS DESIGN

  2019 — 2021