Ashish Kota

WORK HISTORY

EDUCATION

ABOUT ASHISH KOTA

I’m an STA & Synthesis Engineer with strong experience in full-chip timing analysis and interface timing for Multi-SoC (MSoC) designs. With a solid foundation in digital design and advanced node technologies, I’ve played a key role in ensuring timing integrity and driving tapeout success at 7nm and 6nm nodes. Key Skills and Achievements • Expertise in Static Timing Analysis (STA), Synthesis, and full-chip signoff • Hands-on experience with SDC promotion, equivalence validation, and constraint alignment using Excellicon • Successfully completed two full-chip tapeouts for AMD through Terascale Technologies • Proficient in TCL scripting for PrimeTime automation and Python for data extraction and analysis • Familiar with DMSA, LEC, CLP, ECO flows, and Synopsys/Cadence tools including PrimeTime, DC Compiler, Formality, and Conformal I began my career as an SAP BPC Consultant at LTI Infotech, where I led cross-functional digital transformation initiatives. My passion for VLSI led me to transition into semiconductor design, joining Terascale Technologies as an STA & Synthesis Engineer for AMD. Here, I’ve built and analyzed Multi-SoC designs, contributed to critical signoff stages, and worked closely with design teams to resolve timing challenges. I’m committed to continuous learning and have upskilled through advanced VLSI and DFT certifications. I actively explore scripting automation and design methodologies to improve efficiency and timing closure processes. Beyond engineering, I’ve led innovation initiatives as Tech Head of my college’s Robotics & Innovations Club. I enjoy building and participating in tech fests, and I bring that same curiosity and leadership into my professional work. I’m currently open to new opportunities in STA and Synthesis domains where I can contribute to cutting-edge semiconductor design and expand my expertise in physical design, automation, and signoff methodologies.