Ashish Banga

Verification Engineer

Role
Verification Engineer at Microsoft
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Ashish Banga

I have 9+ years of experience in IP Design/Subsystem Verification, developing Testbenches using UVM methodology.

Experience

  1. Verification Engineer

    Microsoft

    Mar 2026 — Present · Hyderabad, IN

Education

  • Netaji Subhas Institute of Technology

    Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

    2008 — 2012

Skills

  • C++
  • Systemverilog
  • Matlab
  • Functional Verification
  • Computer Architecture
  • Perl
  • Embedded Systems
  • C
  • Asic
  • Assertion Based Verification
  • Rtl Design
  • Microprocessors
  • Uvm
  • Modelsim
  • Verilog
  • Universal Verification Methodology (Uvm)
  • Very-Large-Scale Integration (Vlsi)
  • Vhdl
  • Simulations
  • Debugging
  • Vlsi
  • Algorithms
  • Cmos

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Ashish Banga — Verification Engineer at Microsoft in Hyderabad, TG, IN | Unifers