Ashish Agrawal
Senior Principal Design Engineer at Cadence Design Systems
- Role
- Senior Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ashish Agrawal
My aim is to work in a healthy professional environment and to become the best designer.Protocols : I2C, SPI, AMBA AXI, AHB, APB 2.0, BT656 RTL Coding Languages : System Verilog, Verilog, VHDLTechnical Skills: Digital Design Micro-architecture, RTL coding, Lint, CDC, Synthesis, LEC, timing analysis etcHighly experienced in multi-domain clock designs and high speed designs
Experience
Senior Principal Design Engineer
Jul 2024 — Present · Bengaluru, IN
Education
Devi Ahilya Vishwavidyalaya (IET-DAVV)
Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering
2008 — 2012
Skills
- Spi
- Amba Ahb
- Fpga
- Asic
- Field-Programmable Gate Arrays (Fpga)
- Amba Axi
- I2c
- Microcontrollers
- Cmos
- Micro Architecture Development
- Eda
- Vlsi
- Vhdl
- Static Timing Analysis
- Rtl Design
- Spyglass
- Amba Apb
- Verilog
- Matlab
- Very-Large-Scale Integration (Vlsi)
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