Ashish Aggarwal

About Ashish Aggarwal

Senior Engineer, NVIDIA (Santa Clara) 7yrs Senior Engineer, Qualcomm (San Diego)…

Experience

1. Senior Design Verification Engineer, Gpu Hw, Nvidia

   NVIDIA

   Sep 2015 — Present

   Worked on GPU compute core - Streaming Multiprocessor (SM)- design verification across 4 different generations. Worked on all phases from initial feature planning, testplanning, stimulus activation, testbench architecture, checker/reference model setup, supporting tools development to track progress (CI/CD + bug hunting), coverage closure. Developed random testing infrastructure to test the SIMT. These included context driven arbitrary length traces with new Instruction Set Architecture (ISA), reference models, C simulation models, RTL models, HW emulators and real hardware. Responsible for writing, reviewing and executing verification test plans. Streamlined several processes across different teams to keep up with challenging design needs, and ever changing design feature requirements. These include automated processes to track: tracking bugs across different aspects, tracking regressions with different aspects, linking bugs to regressions, tracking coverage and testplans more efficiently. In addition, worked on ML/DeepLearning infra to be able to learn from existing regression/TB infra, how to direct random tests toward finding more bugs in design without user input.

Skills

• Amba Ahb, Axi, Ace
• I2c and I2s
• Microcontrollers
• Verilog
• Formal Verification
• Digital Signal Processors
• C
• Systemc
• Modelsim
• Arm
• C++
• Usb3.0
• Open Verification Methodology
• Mixed Signal
• Simulations
• Mipi Slimbus and Soundwire
• Asic
• I2c
• Algorithms
• Gls
• Perl
• Amba Ahb
• Ic
• Tcl
• Usb
• Rtl Design
• Eda
• Rtl Coding
• Filter Design
• Vlsi
• Jtag
• Functional Verification
• Processors
• Ncsim
• Embedded Systems
• Vhdl
• Uvm
• Soc
• Debugging
• Systemverilog