Asheesh Malviya
Graduate Student in Computer Engineering | Seeking Full-Time Physical Design Engineer Role | ASIC/SoC RTL-to-GDSII Flow | Synopsys & Cadence Tools
- Role
- Physical Design Engineer Trainee at Vlsiguru Training Institute
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Asheesh Malviya
Passionate Computer Engineering graduate student specializing in VLSI Physical Design and ASIC/SoC development. Proficient in RTL-to-GDSII flow, with hands-on experience in:• Floorplanning, placement, and routing• Clock Tree Synthesis (CTS)• Power planning and optimization• Static Timing Analysis (STA)• Design Rule Checking (DRC) and Layout vs. Schematic (LVS)Skilled in industry-standard EDA tools including Synopsys (Design Compiler, IC Compiler) and Cadence (Innovus, Virtuoso) and Ansys(Redhawk-SC).Dedicated to optimizing chip performance, power efficiency, and area (PPA) in advanced technology nodes. Eager to contribute to cutting-edge semiconductor projects and push the boundaries of integrated circuit design.Actively seeking full-time opportunities in Physical Design Engineering to apply my academic knowledge and drive innovation in the semiconductor industry.
Experience
Physical Design Engineer Trainee
Dec 2024 — Present
Education
Sri Bhagawan Mahaveer Jain College
Pre University
2016 — 2018
North Carolina State University
Master of Science - MS
2023 — 2025
BNM Institute Of Technology
Bachelor's degree
2018 — 2022
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