Ashbin P Babu

About Ashbin P Babu

Senior Hardware Design Engineer with extensive experience in server motherboard and system-level hardware design for enterprise and data center platforms. Strong background in end-to-end hardware development, from architecture definition and schematic design to PCB layout reviews, board bring-up, validation, and production support.I have hands-on experience with next-generation server technologies, including PCIe Gen6, DDR5, and CXL 3.0, as well as control and management interfaces such as I²C, SPI, SMBus, and GPIO. I work closely with BIOS, BMC, and firmware teams to ensure reliable hardware–software integration and platform stability.My technical expertise includes:Processor platforms: Intel Ice Lake-SP, Sapphire Rapids, Intel DMRPower electronics: PMIC and power tree design, PWM controller configuration, sequencing, and power integrityFPGA/CPLD development: Verilog coding, reset and power-good logicSignal Integrity and Power Integrity (SI/PI) simulationsBoard-level and system-level debug and validation using standard laboratory equipmentEMI/EMC awareness, pre-compliance debugging, and system-level considerationsComponent selection, BOM ownership, and manufacturing supportI collaborate closely with mechanical and thermal engineering teams on chassis design, airflow optimisation, and thermal simulations, ensuring compliance with reliability and environmental requirements.Currently involved in the development of advanced server platforms based on Intel DMR processors, contributing across hardware architecture, bring-up, and system validation.

Experience

1. Scientist-d

   Centre For Development Of Telematics C-Dot

   May 2023 — Present · Bengaluru, IN

   Intel DMR Based Sever Design•M-SDNO and OCP based server and HPM Design • Board Bringup of Sever Motherboard and Viraj-100 Server System• Viraj-100 showcased at IMC\'24• Inputs to AMI for development of AST2500 BMC Firmware • Inputs to AMI for development of Custom BIOS for the server•Intel VRTT Based Load Testing • PWM Controller configuration for Improving Transient Response of Processor Rails• Implementation of OCP 3.0 in Verilog

Education

• National Institute of Technology Calicut

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2013 — 2017

Skills

• Digital Designs
• C
• Programming
• Xilinx Ise
• Latex
• Digital Communication
• Project Management
• Research
• Cadence Virtuoso
• Matlab
• Mips Assembly
• Arm Assembly
• Wireshark
• Systemverilog
• Questa
• Social Media
• Proteus
• Microsoft Office
• C++
• Spice
• Embedded C
• Leadership
• Linux
• Modelsim
• Shell Scripting
• Verilog
• Microsoft Excel
• Vhdl
• Computer Network Operations
• X86 Assembly
• Perl