Asha Lata
Senior Design Engineer at AMD , Physical Design
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Asha Lata
PNR and block level implementation floorplan, powerplan, placement, cts, routing, GDS-II, Physical verification. Drcs and LVS clean up. Congestion analysis with rectification IR analysis for both static and dynamic power. Power Grid analysis.
Experience
Senior Silicon Design Engineer
Jun 2022 — Present · Bengaluru, IN
Education
Maharshi Dayanand University
Bachelor’s Degree, Electronics and Communications Engineering
2006 — 2009
GITM Gurgaon campus
Master’s Degree, Electronics and Communications Engineering
2011 — 2013
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