Aseem Verma

About Aseem Verma

TFM (Tools, Flows, Methodology) Engineer offering expertise in backend physical design to ensure successful project execution with high quality. Developing new concepts, flows and deploying those capabilities across different teams.Over 16 years of experience in developing, delivering and supporting backend flows and design methodologies. Having a rich EDA experience of pre and post-sales support, managing AE team and handling critical account.Extensive hands-on technical experience in Floorplan Tech Readiness, Synthesis, APR, PPA exploration and custom CTS methodologies. End to end flow deployment and ownership in advance nodes for internal and external customers.

Experience

1. Pmts Silicon Design Engineer

   AMD

   Dec 2023 — Present · Bengaluru, IN

Education

• RGPV, Bhopal, India

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  1999 — 2004

• DAIICT, Gandhinagar, India

  M.Tech, VLSI

  2004 — 2006

Skills

• Signal Integrity
• Vlsi
• Ddr
• Tcl
• Soc
• Logic Design
• Physical Design
• Formal Verification
• Static Timing Analysis
• Perl
• Eda
• Cmos
• Cadence Virtuoso
• Debugging
• Verilog
• Timing Closure
• Low-Power Design
• Integrated Circuit Design
• Logic Synthesis
• Rtl Design
• Fpga
• Asic
• Dft
• Ic
• Timing
• Functional Verification