Ajay Bisht

EDA Software Professional | Low Power | Power Analysis | Power Optimization | Machine Learning Developer

Role
Senior Director, R & d Engineering at Synopsys Inc
Location
San Jose, CA, US
LinkedIn followers
500 followers

About Ajay Bisht

Strong technical skills with extensive hands-on and skilled software development management in a fast paced customer-driven environment. Demonstrated strong expertise in architecting, solving complex problems and driving engineering efforts with an excellent track record of progressive management responsibility for over 22 years. Subject matter expert in the areas of Chip Power Analysis and Optimization, Principal architect for RTL/Gate power analysis and optimization tools in industry– PowerArtist and Joules Competent in Test-driven software development using C/C++, STL, Python Hands-on exposure to Machine Learning and data-analysis packages such as NumPy, Pandas, Scikit-learn, TensorFlow and Keras

Experience

  1. Senior Director, R & d Engineering

    Synopsys Inc

    Feb 2024 — Present · Sunnyvale, CA, US

Education

  • UCSC Silicon Valley Extension

    Physical Design Flow From Netlist to GDSII, VLSI Engineering

    2014 — 2014

  • Indian Institute of Technology, Kharagpur

    Master of Technology, Computer Science & Engineering

    2001 — 2003

  • Saraswati Bal Mandir, Punjabi Bagh, New Delhi

    SSE

    1990 — 1995

  • Kumaun University, Nainital

    Bachelor of Engineering, Computer Science & Engineering

    1997 — 2001

  • SBM, Hari Nagar, New Delhi

    AISSCE, English, Mathematics, Biology, Chemistry, Physics

    1995 — 1997

Skills

  • Debugging
  • Vhdl
  • Simulations
  • Low-Power Design
  • Static Timing Analysis
  • C++
  • Vlsi
  • Modelsim
  • Ic
  • Algorithms
  • Logic Synthesis
  • Soc
  • Semiconductors
  • Functional Verification
  • Oop
  • Systemverilog
  • Programming

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Ajay Bisht — Senior Director, R & d Engineering at Synopsys Inc in San Jose, CA, US | Unifers