Amisha Sankhwar
Design Implementation (Synthesis) | Static Timing Analysis (STA) | ASIC Timing Closure | Pre & Post-STA | Synopsys DC & PrimeTime | M.Tech’22 @ MNIT
- Role
- Synthesis & Sta Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Amisha Sankhwar
STA & Synthesis Engineer with experience in advanced-node SoC designs (6nm/7nm) and block-level timing closure.• Hands-on in logic synthesis and physical aware synthesis, along with pre-layout and post-layout STA using Synopsys Design Compiler & PrimeTime.• Strong exposure to sign-off timing analysis, constraint validation, and multi-mode multi-corner timing checks.• Experience working on high-speed interface and multimedia blocks, contributing to timing optimization and ECO cycles.• Proficient in SDC debugging, LEC & CLP checks, and timing closure using DMSA and manual optimization techniques.• Skilled in Tcl scripting and constraint-quality checks to automate STA flows and improve timing predictability.
Experience
Synthesis & Sta Engineer
Sep 2022 — Present · Hyderabad, IN
Education
Malaviya National Institute of Technology Jaipur
Master of Technology - MTech, Electrical, Electronics and Communications Engineering
2020 — 2022
Dr. A.P.J. Abdul Kalam Technical University
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
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