Asangeppa Hadimani
Physical Design Integration Engineer at intel corporation.
- Role
- Physical Design Integration Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Asangeppa Hadimani
Excellent knowledge in field of Physical Design, STA, Physical Verification.* Worked on different technology nodes (14A,18A,3nm, 7nm,10nm,10++nm,14nm)*Hands on experience with latest TSMC/Intel chip design process like 14A, 18A, 3nm,5nm, 7nm,10nm and 14nm technologies.*Block level Implementation which includes Synthesis, Floor-planning, Power Planning, Placement, CTS, Routing, timing closure, Quality fixes and other signoff checks.* Good knowledge on RibbonFET [Gate All-Around Transistors (GAA)], Back-side power or nano TSV or Power VIA technology.* Real time work experience in DRC, LVS, ERC, DFM, MRC, Antenna, LU, dfi_integra, MIN/MAX Density *Hands on experience physical design, physical verification of Multiple complex IP\'s, Subsystems and SOC * Taken responsibilities like reviewing Final Checks for Physical Verification Sign off and training for new joiners.
Experience
Physical Design Integration Engineer
Nov 2023 — Present · Bengaluru, IN
Education
International Institute of Information Technology Bangalore
Post Graduate Diploma
2015 — 2016
Dayananda Sagar College of Engineering, BANGALORE
Bachelor's degree
2011 — 2014
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