Arvind Ramakrishnan
Staff Design Verification Engineer @新思國際科技有限公司
San Francisco, CA, US
EMAILS
a••••••••@synaptics.com
MOBILE NUMBERS
+14•••••••08
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WORK HISTORY
Dec 2017 — Present
Staff Design Verification Engineer @新思國際科技有限公司
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Working on SOC Verification for IOT chipsets.
SKILLS
ModelsimAssemblyUvmC++Very-Large-Scale Integration (Vlsi)CadenceCircuit DesignSystemverilogSimulation SoftwareRtl DesignMatlabVlsiPerlCadence VirtuosoVerilogSimulations
ABOUT ARVIND RAMAKRISHNAN
Technically accomplished professional with 6+ years of experience in system-verilog and…
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