Arvind Ramakrishnan
- Role
- Staff Design Verification Engineer at 新思國際科技有限公司
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Arvind Ramakrishnan
Technically accomplished professional with 6+ years of experience in system-verilog and…
Experience
Staff Design Verification Engineer
Dec 2017 — Present
Working on SOC Verification for IOT chipsets.
Skills
- Modelsim
- Assembly
- Uvm
- C++
- Very-Large-Scale Integration (Vlsi)
- Cadence
- Circuit Design
- Systemverilog
- Simulation Software
- Rtl Design
- Matlab
- Vlsi
- Perl
- Cadence Virtuoso
- Verilog
- Simulations
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