Arvind C.

About Arvind C.

A senior engineering leader with 24+ years of experience driving verification strategy, methodology development, and execution across complex ASIC, FPGA, and SoC programs. Expertise spans UVM/OVM SystemVerilog environments, coverage‑driven verification, and protocols such as PCIe, AXI, DMA, and TCP/IP, alongside extensive FPGA IP and Vivado‑based development. More than 15 years of building verification environments from the ground up and over 7 years leading high‑performing teams contribute to a strong focus on modernizing DV methodologies, advancing shift‑left initiatives, improving EDA flows, and enabling organizations to deliver robust, high‑quality silicon and FPGA solutions on schedule.

Experience

1. Sr Principal Design Verification Lead

   TrendAI

   Jan 2025 — Present · Austin, TX, US

Education

• New Jersey Institute of Technology

  Computer Hardware Engineering