Arun K.

About Arun K.

Domain Expertise:* Products - PSoC (Programmable System On Chip), SRAM, FLASH, NV-SRAM, DRAM, Image Sensor, etc.* Design flow and tools development, automation and support.* Design Implementation - Synthesis, Place and Route ( PnR ), STA and Layout/mask design - Full-chip and IP\'s block level design, verification and Tapeout. IP\'s P&R, STA, IR and EM analysis * Standard Cell Libraries/IO cells development and Characterization.* PDK developement of DRC, LVS PEX rule deck development, models validation, etc.* Project Management and team management.* People management - Hiring,Team setup,Training/mentoring, performance reviews, career planning.* Consultancy, Training and Business Development EDA tools: Cadence – Innovus, SoC EDI, Conformal, Virtuoso, Composer, Assura, Diva, Dracula, etc Synopsys – IC-Compiler, Astro, PT, PT-SI, etc Mentor Graphics – Calibre, Tessent, Questa Formal & Static etc Scripting: Skill, Shell, Perl, Python and Tcl

Experience

1. Principal Engineer

   onsemi

   Oct 2018 — Present · Bengaluru, IN

   Extensively involved in Digital Design Implementation tool flow development and implementation. This include all RTL 2 GDS design stages. Including RTL validation ( lint, dft, cdc, etc.), Synthesis, Place and Route, STA, Power, EM & IR and Physical verification. EDA tool QA and benchmarking, Training and support.

Education

• Karnatak University

  B.E.

  1983 — 1988

Skills

• Asic
• Soc
• Timing Closure
• Static Timing Analysis
• Integrated Circuit Design
• Vlsi
• Project Management
• Mixed Signal
• Physical Design
• Drc
• Perl
• Eda
• Lvs
• Cadence
• Physical Verification
• Tcl
• Place & Route