Arunkumar Bm
Physical Design Engineer at Intel Corporation
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Arunkumar Bm
Technical Summary Worked on Physical Implementation of block starting from RTL to GDS, including Synthesis, Floor planning, Place and Route, CTS, Timing Analysis, Timing closure, DRC/LVS and sign off. Worked on 28nm, 14nm,10nm,7nm & TSMC 3nm Technologies. Resolving various Block level PnR issues. Understanding of Reliability issues like EM, Cross-talk, and Antenna effect. Good knowledge of EDA tools from Synopsys’s ICC2, DC Compiler, IC Complier, Prime Time, VCLP and Apache’s Redhawk. Experience with Industry Standard, Cheetha flow, RDT flow Makefile and Script based Physical Design flow - Floor planning, Placement, Clock Tree Synthesis and Routing. Able to Understand the Industry flow & TCL Sripts.
Experience
Soc Design Engineer
Jul 2021 — Present · Bengaluru, IN
Education
Nagarjuna College Of Engineering and Technology
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2013 — 2017
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