Arun K
Analog Layout Engineer @HCLTech
- Role
- Analog Layout Engineer at HCLTech
- Location
- Chennai, TN, IN
- LinkedIn followers
- 500 followers
About Arun K
As a passionate Electronics and Communication Engineer and a VLSI enthusiast, I have a keen interest in Analog and Mixed Signal Layout design and Memory design.Proven experience in CADENCE VIRTUOSO and LTspice softwares ranging from 90nm to 5 nm FinFET and MosFET technologies.Proficiency in virtuoso ADE (transient, parametric dc, delay and power ) analyses of standard cells, Layout L,XL (matching, shielding, floorplan, LVS, DRC) techniques.Hands-on layout experience in digital blocks such as standard cells and analog blocks such as current mirrors, error amplifier, differential pairs, folded cascode OTA, Bandgap reference, Low dropout regulator, power MosFETs, etc.
Experience
Analog Layout Engineer
Mar 2025 — Present
Education
Easwari Engineering College(SRM Group)
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2020 — 2024
Morning Star Matriculation Higher Secondary School
Biology, Mathematics
2014 — 2020
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