Arunay Kaushik
Senior Lead-ams Verification @NXP Semiconductors
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WORK HISTORY
Senior Lead-ams Verification @NXP Semiconductors
Bengaluru, IN
Building Best-in-class Mixed Signal Products for the World.Working on Modeling and Verification across Mobile, Industrial and IoT semiconductor products.1. Low Voltage IO Aggregator for premium smartphone manufacturerAn aggregator designed to reduce the number of cables inside foldable/mobile devices. It supports I2C, I3C and SPI protocol to transfer data between Upstream SoC and Downstream low frequency peripherals like fingerprint, sensor, touch, camera, charger etc.Product will be extended to VR headsets and server segment.2. Universal Input AFE for industrial applicationsHigh precision AI-AFE platformContains 13 bit DAC and 16/24 bit ADCDifferential analog input in the range +/-23VThermal protection, self-calibration, wide supply range +/-32VAdvanced diagnostics features
EDUCATION
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, VLSI Design and Microelectronics
Kendriya Vidyalaya NTPC Korba C.G.
AISSCE, Maths, Science
Shri Shankaracharya Technical Campus
Bachelor of Engineering - BE, Electronics & Telecommunication
CDAC ACTS Pune
Post Graduate Diploma, Very Large Scale Integration(VLSI)
SKILLS
ABOUT ARUNAY KAUSHIK
Professional Summary:I am a Senior Lead AMS Verification Engineer with over 12.8 years of experience specializing in the behavioral modeling and verification of complex mixed-signal designs. Delivered bug-free silicon and achieved successful tape-outs for high-performance IPs and SoCs across multiple process nodes.I offer a deep technical breadth in architecting unified test environments for full-chip complex SoCs, whether the architecture is Digital-on-top or Analog-on-top. My expertise lies in bridging the gap between spice-level accuracy and SoC-level simulation speed through advanced Analog and Real Number Modeling.Mixed-Signal Domain Expertise:• Technical Breadth: Proven track record with a wide range of AMS IPs, including ADC, DAC, PLL, Digital Voltage Regulators (DFIVR), LDOs, Thermal Sensors, and Bandgap references. • Advanced Modeling: Expert in SystemVerilog RNM, Verilog-AMS, Verilog-A, and Wreal modeling to ensure rigorous model vs. schematic verification. • Power-Aware Verification: Proficient in Low Power simulation (UPF), writing UPF specifications, and executing power-aware mixed-mode simulations. • Tool Mastery: Hands-on command of the Cadence AMS Suite (Xcelium, SpectreX, vManager) and Synopsys Tool Suite (VCS XA, Verdi, Custom Waveview). • Flow Automation: Streamlining verification tasks through scripting in SKILL, Shell, PERL, and Python.Throughout my tenure at industry leaders like NXP, Intel, Global Foundries, and Qualcomm, I have transitioned from technical execution to leading high-impact teams, mentoring junior engineers on efficient verification methodologies and UPF-compliant modeling.Core Competencies: AMS Verification | SV RNM | Analog Behavioral Modeling | SoC Co-simulation | Low Power (UPF)| Mixed-Signal IP Sign-off | Technical Leadership
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