Arun Vaishnav
DV Engineer @ Wipro | SystemVerilog | UVM | SoC Verification | PCIe | RTL Debug
- Role
- Dv Engineer - Software L2 at Wipro
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Arun Vaishnav
About MeHello! I’m a dedicated Design Verification Engineer based in Hyderabad, India. Technical SkillsExpertise in Electronics Engineering with a strong foundation in digital system design and verification-> HDL: Verilog-> HVL: SystemVerilog-> Scripting Language: Python-> Programming Language: C++-> Verification Methodology: UVM-> Tools: Synopsys VCS, CASA Verdi-> Verification Concepts: SV code and functional coverage, SV assertions, testcase writing-> Protocols: AMBA AXI, APB, AHB, I2C, SPI, UART-> Theory: ASIC Design/Verification, CPU Design, Computer Architecture, Digital Logic Design, System IP Validation, Functional Verification 🤝 Open to OpportunitiesI am keen to connect with professionals from the VLSI and semiconductor sectors. If you’re in these industries, I would love to hear from you. Let’s connect and explore potential collaborations or just have an enriching conversation!
Experience
Dv Engineer - Software L2
Jul 2024 — Present · Hyderabad, IN
Developed and debugged UVM-based testbench components such as scoreboard, coverage collector, sequences, assertions, driver, and monitor to ensure robust verification infrastructure • Automated log analysis by developing Python scripts to extract and interpret packet-level data from simulation outputs • Implemented protocol trackers in Python to verify compliance and trace protocol behavior throughout simulation • Identified RTL and testbench issues using Verdi, improving simulation stability and coverage closure • Created detailed and structured test plans aligned with design specifications and verification goals
Education
MBM Engineering College, Jodhpur
Bachelor of Engineering, Electrical and Electronics Engineering
M.B.M. Engineering College, Jodhpur
Bachelor's degree, Electrical and Electronics Engineering
2017 — 2021
LALA KAILASHPAT SINGHANIA PUBLIC SCHOOL
12th, Physics, Mathematics and Chemistry
NPTEL IIT Guwahati
System Design Through Verilog, Course
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