Arun Sundaram

About Arun Sundaram

RTL synthesis to GDS, worked in 45nm, 40nm, 28nm, 20nm architecture and 16ff, 10lpe, 7ff and IOT devicesSpecialties: Physical design, CAD Methodology.

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Oct 2007 — Present · Bengaluru, IN

   Managed & led high performance teams, responsible for multiple ramp-up of high performance teams, project execution support A dedicated team player and leader with strong technical, communications, project management and inter-personal skills Energetic and highly motivated technical professional with expertise in building and leading collaborative teams Extensive global customer interactions & fulfillment Cross-site /geo & cross functional leadership experience Strong communication, interpersonal and leadership skills Collaborate and communicate technical design and priorities with SOC, Hard Macro and IP teams Lead and hands-on approach to resolve critical SOC physical design issues Involved in methodology for estimating, optimizing and co-relating Power, Performance and Area (PPA) of High Performance and low power SOC’s Involved in Physical design timing closure activities for multiple tape outs across all technologies (40nm, 28nm, 20nm, 16ff, 14ff, 10lp, 8lpp, 7ff, 5lpe,4lpx,4ff)

Education

• Bangalore University

  BE EE, Electrical& Electronics

  1998

Skills

• Static Timing Analysis
• Vlsi
• Physical Design
• Processors
• Cmos
• Fpga
• Asic
• Functional Verification
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Ic
• Primetime
• Tcl
• Rtl Design
• Timing Closure
• Field-Programmable Gate Arrays (Fpga)
• Soc
• Verilog
• Logic Synthesis
• System on a Chip (Soc)
• Very-Large-Scale Integration (Vlsi)
• Low-Power Design
• Eda