Arun Seetharaman

About Arun Seetharaman

Extensive experience across Digital circuit design, Physical Design, and Timing convergence. Recognized consistently for performance excellence and contributions to success in the VLSI industry. Passionate about technology - As a Technically hands on Engineering Leader driving innovation across design and optimization in digital circuit design An acknowledged mentor and leader with a proven track record of bringing budding design engineers to become independent and move to the next level in the technical ladder.Currently, Responsible for driving CPU implementations on latest ARM CPUs on 5nm & lower technologies for Infra/Client segments, close engagement with EDA vendors & Physical IP product teams for developing the best in class flows & physical IPs, PPA data creation for marketing teams, etcBefore joining ARM, I was leading the digital circuit design work on Intel microprocessor core on the latest sub-micron technology. My core area of expertise includes- RTL->GDSII in digital circuit design- Gate Level Synthesis- Design for speed to meet high-performance Processor frequency.Before joining Intel, I was leading the Full Chip Floorplanning for in Qualcomm for the latest mobile SOC\'s, responsible for achieving best in class floorplan with minimal die size and robust power grid which meets both timing as well as IR requirements.My responsibilities included close interaction with multiple IP/Packaging teams to come with the optimal floorplan as well.Also worked with Standard Cell and Memory teams in defining and optimizing the design at standard cell and macro level.Before joining Qualcomm, I was a working on digital circuit implementation of High Speed Networking SOC\'s at Freescale Semiconductor for achieving best in class PPAEDA Tools Exposure: 1) Physical Design: SOC Encounter(Cadence) Innovus(Cadence) Olympus(Mentor) IC Compiler(Synopsys) IC Compiler ||(Synopsys)2) Signal Integrity analysis: Clarinet,Celtic(Cadence),PT-SI(Synopsys),Voltus(Cadence)3) Extraction: QRC(Cadence),STARRC(Synopsys),Quantus(Cadence)4) Static Timing Analysis: CTE (cadence),ETS(cadence),PT(Synospys),Tempus(Cadence)5) Logic equivalence checking:Conformal LEC(Cadence),Formality(Synopsys)6) Synthesis: RTL Compiler(Cadence),Design Complier(Synopsys),Genus(Cadence)7)Physical Verification:Calibre(Mentor)Scripting Languages: TclSpecialties:CPU implementations for Fmax, low-power specifications, PPA estimations, Physical IP tuning, EDA engagements.

Experience

1. Director R & d

   新思科技股份有限公司

   Mar 2024 — Present · Bengaluru, IN

   Building and Leading the Foundry R&D Ecosystem team in India.My responsibilities include Hiring,Team building and integration,Driving key strategic initiatives across foundries, technical and people management etc

Education

• Delhi Public School - R. K. Puram

  SCIENCE

  1992 — 2002

• Anna University Chennai

  B.E, ELECTRONICS & COMMUNICATION

  2002 — 2006