Arun Prabhakaran

Experience

1. Sr Staff Design Engineer

   Intel

   Dec 2002 — Present · CA, US

   Technical Lead driving Implementation and Timing convergence across the team and a consultant for the larger team- Designed and Delivered multiple power management IPs to 20+ customers spanning multiple SoCs meeting all the requirements of each and every customer- Lead the Floorplan convergence of the high frequency core-interface subsystem interfacing with partition and soc customers- Lead the timing closure of an embedded soc on the first xeon based microserver from rtl to tapeout in 8 months- Lead the timing convergence and re-floorplan of memory controller and cache coherency controller sections at multiple voltages. Drove die cost reduction by re-floorplan of these 2 sections- Lead the timing convergence of a high frequency core-interface section on a multicore cpu- Collaborated with multiple cpu teams to converge on a reduced common set of radiation hardened sequential library- Managed a team of designers to drive the final tapeout quality block convergence on the core-interface section- Designed multiple custom and compiler based register files and the associated building blocks

Education

• College of Engineering, Chengannur, Kerala, India

  Bachelor of Technology (B.Tech.), B. Tech Electronics

  1994 — 1998

• Cochin University of Science and Technology

  M. Tech Electronics, Digital Electronics

  1998 — 2000

Skills

• Full Chip Timing Convergence
• Physical Integration
• Soc
• Tcl
• Physical Design
• Perl
• Vlsi
• Static Timing Analysis
• Asic
• Verilog
• Synopsys Primetime
• Semiconductors
• Microprocessors
• Pt-Si
• Register Files
• Soft Error
• Timing Closure
• Integrated Circuit Design
• Ic
• Processors
• Eda
• Debugging
• Spice
• Systemverilog
• Very-Large-Scale Integration (Vlsi)