Arun Kumar Reddy Yaramala
ASIC Design Verification Engineer- Incise infotech
- Role
- Design Verification Engineer at Qualcomm
- Location
- Vijayawada, AP, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Arun Kumar Reddy Yaramala
My skill set includes Verilog, System Verilog, Universal Verification Methodology(UVM), Assertion based Verification, Coverage, Power Aware sims.
Experience
Design Verification Engineer
Jun 2024 — Present · Chennai, IN
Contractor
Education
Lakireddy Bali Reddy College of Engineering(Autonomous)
Bachelor of Technology - BTech, Electronics and communication engineering
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