Arulnesan V

About Arulnesan V

Around 12+ years of strong experience in VLSI Front-End Design and Verification and having good knowledge in Verilog,SystemVerilog, VHDL and basic knowledge in SystemC,Specman e, and scripting language like perl.Knowledge in ARM debug infrastructure and protocols(DAP,CTI/CTM,ATB) and Crash debug,Scandump,Memdump.DCC, Processor and Co-Processor, DFT, Ethernet 802.3, 802.11n,ARM JTAG and bus/communication protocols like AMBA,SPI, I2C,McASP,QSSI,LPC-UART,FAN-CONTROLLER.Expertise in setting up Verification environment in Verilog, Specman,OVM/UVM for IP Level and SOC level. Good team worker and quality team builder. Hands on experience in APB,JTAG VIP development using UVM.Area of Interest and willing to learn/work on- Unique verification environment for IP level to Silicon/FPGA Verification - Debugger infra, CPU infra, IoT,Robotics,Image processing- Artificial intelligent on verification.

Experience

1. Senior Staff Engineer

   Qualcomm

   Dec 2024 — Present · Bengaluru, IN

Education

• Sudharsan Engineering College

  BE, Electronics and Communication Engineering

  2003 — 2007

• Muvendar Matriculation Hr. Sec school

  HSS, Mathematics

  2001 — 2003

Skills

• Logic Synthesis
• Physical Design
• Cadence Virtuoso
• Xilinx Ise
• Functional Verification
• Systemc
• Spi
• Amba Ahb
• Rtl Coding
• Uvm
• Jtag
• Debugging
• C
• Arm
• Uart
• I2c
• Vhdl
• Specman
• Usb
• Lvs
• Perl Script
• Logic Design
• Timing Closure
• Integrated Circuit Design
• Microprocessors
• Signal Integrity
• Fpga
• Soc
• Asic
• Tcl
• Digital Signal Processors
• Formal Verification
• Ncsim
• Drc
• Dft
• Modelsim
• Static Timing Analysis
• Digital Electronics
• Ethernet
• Open Verification Methodology