Arti Bhanushali
Senior Verification Engineer @Riverlane
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WORK HISTORY
Senior Verification Engineer @Riverlane
Cambridge, GB
EDUCATION
Ganpat University
Diploma, Electronics and Communications Engineering
Dhirubhai Ambani University
Master of Technology (M.Tech.), VLSI and Embedded Systems
Ganpat University
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
ABOUT ARTI BHANUSHALI
Senior ASIC/SoC Verification Engineer with nearly 8 years of experience in IP and SoC verification. Specialized in SystemVerilog, UVM, C, and protocols like PCIe, AXI4 and APB. Familiar with ARM architecture and NVIC. Skilled in handling the complete verification cycle—from test planning to coverage closure.My Experience includes leading verification projects, reusable UVM-based testbench development, constrained random verification, functional and code coverage analysis, assertion-based verification (SVA), and thorough debugging. Well-versed with EDA tools such as VCS, Verdi, Xcelium, SimVision, and Questasim. Also experienced in VIP development and mentoring junior engineers.
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