Arrush Hegde
Physical Design Engineer
- Role
- Design Engineer 2 at Cadence
- Location
- Fort Collins, CO, US
- LinkedIn followers
- 500 followers
About Arrush Hegde
Hardworking Electrical Engineer with profound knowledge in VLSI/ASIC design. Working as a circuit design engineer. Looking to switch to Physical Design-Currently working in the SRAM circuit design team for AMD as a Silicon Design Engineer-Designed and owned 7nm silicon based high speed (>4GHz) custom 256-bit SRAM Data and Tag macros for the L3 cache-Collaborated with layout, RTL and Physical Design Engineers in ensuring tapeout-Researched, designed and tested a 128-bit latch array in advanced FinFET processes (<7nm). Used clock gating and clock shaping techniques to minimize power while meeting setup and hold requirements-Worked on STA, functionality, power, EMIR and assist features to meet required results using Synopsys and Cadence tools- Published a paper on Security Specification Language in 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). Link: Email id: a••••••••@gmail.com
Experience
Design Engineer 2
Mar 2023 — Present · US
Education
Vellore Institute of Technology
Bachelor of Technology - BTech, Electrical and Electronics Engineering, 7.45
2013 — 2017
University of Florida
Master of Science - MS, Electrical and computer engineering
2019 — 2021
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