Arpit Desai
ASIC RTL Design Engineer at Qualcomm
- Role
- Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Arpit Desai
Experienced in Front End Design Execution of complex designs in RTL Domain.HDL : Verilog, System VerilogVerification : SystemVerilog/UVM testbenchesTools: Synopsys VCS, Spyglass, VC-FormalLow Power - UPF, VC-LPArchitecture: ARM32, ARM64Scripting and Automation: Unix/Linux, Shell, Perl, Python, TCL, GIT, Jira, AgileStatic Checks - Lint, CDC, RDC, VC-LP.Areas of Interest: ASIC RTL Design,FPGA Design, Design Verification and Automation.
Experience
Engineer
Mar 2024 — Present · Bengaluru, IN
Mixed Signal IP Digital Design
Education
Visvesvaraya Technological University
BE
2013 — 2017
Vellore Institute of Technology
Master of Technology - MTech
2021 — 2023
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