Arpit Kumar

About Arpit Kumar

My working experience is in ASIC verification. It includes the various requirements like gathering, verification definition, verification environment development (with scoreboards, checkers etc), reusable verification components development using UVM/OVM - System verilog. I have extensively worked on functional/code coverage, Low power transition coverage, verdi planner. Experiences also include on - • Worked on different protocols like TCAM/EDRAM ethernet, SPI, Intel Specific protocol and PCIe gen3 Protocol [TLP layer] for ASICs/SOC at block level and at IP level using System verilog & UVM/OVM/VMM methodologies. Verification planning, environment architecture and component development from scratch and verification with hands on ownership on Sub-system and standalone IP level verification. • Hands on experience in C based verification for CR8, CA55 and CR4 processors respectively.• Hands on experience in Low power verification and Low power transition coverage.• Hands on experience in coverage driven verification, assertion based verification.

Experience

1. Senior Validation Engineer

   Intel

   Jan 2021 — Present · Bangalore Urban, IN

   Owned pre-silicon verification of Soc Ips related to Trace Aggregators, Memory Transaction Observers. Collaborated with Architects/Designers to understand design features and implemented respective scenario in our environment including bringing up the environment for Die to Die connectivity. Handled review metrics and delivered the task with high quality. Leading and tracking verification implementation and execution with technical guidance to team.

Education

• Delhi Public School

  Class 12 th, MATHS

  2003 — 2005

• MIET Gondia

  BE, Electronics and Communications Engineering

  2006 — 2010