Arpit Jain

About Arpit Jain

I have completed my post graduation in June 2017 from the Maulana Azad Nation Institute of Technology Bhopal with a Master of Technology in VLSI and embedded systems. Currently, I am working as manager, layout design with Synopsys inc, hyderabad. I worked as Layout design engineer with Zia semiconductor at the client location i.e. ST Microelctronics Noida. I was an intern at St microelectronics (Noida, India). I was an intern with back-end team of standard cell design. During my internship, my responsibilities included layout design for sequential cells like FF and latch for 28nm and 40nm. I am expertise with design rule checks, layout vs schematics checks, and its physical view generation and design validation for different PVTs. I was responsible for high performance and high density cells. I have also been utilised for research trials and reverse engineering works like layout to schematic design.Regarding my M.tech. project, I am generating a design for body bias generator with the considerations of standard cell, its size, and other constraints. Its core functionality is to generate negative volt for biasing the cells using well tap biasing.I have been summer research fellow for the period of may 2016-june 2016, funded and awarded by Indian academy of sciences at IIT Chennai under the guidance of prof. V. Kamkoti. My responsibility was to design an advanced debug interface with bluespec language.I have completed the bachelor of engineering in July 2013 with Electronics and Communication Engineering discipline from College of Technology And Engineering Udaipur. I had worked as a research fellow in MPUAT Udaipur with a DEITy (Govt. of India) sponsored project for the period of feb.2014- July 2016, related to design and development of a MIMO detector project and its hardware implementation. There, my responsibilities were related to design the algorithms in VHDL, FPGA implementation and co-simulation with MATLAB.

Experience

1. Product Application Engineer

   新思科技股份有限公司

   Mar 2025 — Present

Education

• College of Technology and Engineering , Udaipur

  Bachelor’s Degree, Electrical, Electronics and Communications Engineering

  2009 — 2013

• Maulana Azad National Institute of Technology

  Master’s Degree, VLSI and embedded systems

  2015 — 2017

• Indian Institute of Technology Hyderabad

  Doctor of Philosophy - PhD, AI in VLSI physical design flow

Skills

• Eldo
• Pspice
• Fpga
• Design Rule Checking (Drc)
• Bluespec
• Bash
• Power Analysis
• Static Timing Analysis
• Circuit Design
• Cadence Virtuoso
• Fdsoi
• Vlsi
• Microcontrollers
• Vhdl
• Layout Versus Schematic (Lvs)
• Mimo
• Xilinx Ise
• Rtl Design