Arpit Goyal

About Arpit Goyal

Currently working in Micron technology as Design verification Engineer. Working on DDR5 verification.Maining working on circuit debug using Cadence virtuoso and simivision.Working on scoreboards using SV and UVM and do setup related to Mode register settings, DUT data monitoring.Checking assertions fails.Worked in synaptics Incorporated as ASIC Engineer. I was a member of SoC integration team. In which I worked on Makefile flows and IPXACT files.Did automation using TCL.Done internship in intel in frontend RTL design team.skills-Taking ownership of several flow enablement from RTL-GDS-II.Generating Gate level netlist using Fusion compiler.Debugging RTL using fc_shell and pt_shell.Done Automation using perl script.Checking Logical equivalency of a design using Conformal LEC.Done CDC check for multiple partions using Spyglass CDC by synopsys.Checking quality of RTL using caliber tool.Good knowledge of Verilog and system Verilog, SVA, Functional Coverage and concept of UVM.Done verification of FIFO, SPI, D Flipflop using system Verilog.Done major project of mtech on Santaurus TCAD designed novel structure of Biosensor, photosensor and gas sensor.Have three years of experience in Infosys in SharePoint and Exchange administration.

Experience

1. Senior Verification Engineer

   Micron Technology

   Nov 2025 — Present · Hyderabad, IN

Education

• GLA University

  Bachelor of Technology - BTech, Electronics and Communication

  2014 — 2018

• Malaviya National Institute of Technology Jaipur

  Master of Technology - MTech, VLSI Design