Arpit Bhatnagar
RTL Design Engineer at Semifront Technology Pvt. Ltd.
- Role
- Rtl Design Engineer at Semifront Technologies
- Location
- Panipat, IN
- LinkedIn followers
- 500 followers
About Arpit Bhatnagar
RTL design engineer with experience in Gen 5 PCIe IP Development, SoC integration projects and Functional Safety Analysis.
Experience
Rtl Design Engineer
Jun 2024 — Present · Kolkata, IN
Gen 5.0 PCIe IP Development : Responsible for RTL design of the complete PCIe datapath, from AXI to various PCIe layers and back to AXI, ensuring compliance with Gen 5.0 PCI Express specifications.Designed the entire datapath and simulated in a Dual DUT environment, supporting various configurations with different lane counts and widths.Worked with formal verification team to verify individual datapath sub-blocks to ensure correctness and robustness.Client Projects : Worked on the Functional Safety Analysis of a chip.Worked on SOC integration for a client.
Education
National Institute of Technology, Kurukshetra, Haryana
Bachelor of Technology - BTech
2020 — 2024
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.