Arpan Mougana
Senior DFT Design Engineer @Infineon technologies
- Role
- Senior Dft Design Engineer at Infineon Technologies
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Arpan Mougana
A passionate DFT engineer with a spectrum of experience having strong understanding of concepts,methodologies and issues in DFT. As an engineer loves probing things, facing and solving challenges. My responsibilities include Making design DFT friendly, Scan insertion with compression, ATPG,Boundary scan(1149.1,1149.6),MBIST insertion and validation, Memory repair flow, ICL & Tap validation. test coverage analysis for both stuck at & atspeed, Gate level simulations for both timing and zero delay, Spyglass DRC cleanup, SSN loopback and continuity patterns check.SIB insertion and tdr programming. I had good exposure to STA, automated the work flow with the use of TCL, bash & perl scripting.
Experience
Senior Dft Design Engineer
Feb 2026 — Present · Bengaluru, IN
Education
RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID
B.Tech
2018 — 2022
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