Arpan Jadhav

About Arpan Jadhav

ASIC Verification Experience-• SOC level Verification.• Subsystem level Verification. • IP level Verification. • UVM VIP Verification.ASIC Verification Skill-• HDL: Verilog • HVL: System Verilog• Verification Methodologies: Coverage Driven Constraint Random Verification, Assertion Based Verification. • TB Methodology: UVM• EDA Tool: SimVision, DVE tool, Verdi, Questasim, Xilinx ISE Design tool and Riviera Pro. • Domain: ASIC Design Flow, Digital Design methodologies• Other Knowledge: RTL Coding, FSM based design, Simulation, Synthesis, Code and Functional Coverage, Static Timing Analysis, RAL, Perl.• Protocols: AXI, AHB, APB, SPI, Timer based Protocol & SOC Verification

Experience

1. Lead Engineer

   Qualcomm

   Dec 2023 — Present

Education

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor's degree, VLSI, Electronics and Communication

  2005 — 2009

• SIMS Indore

  Master’s Degree, Embedded System and VLSI Design

  2011 — 2013

Skills

• Static Timing Analysis
• Digital Electronics
• Vlsi
• Register Abstraction Layer(Ral)
• Fpga
• Asic
• Verilog
• Perl
• Electronics
• System Verilog
• Field-Programmable Gate Arrays (Fpga)
• Uvm