Joseph Aronson

About Joseph Aronson

Digital Design Engineer in the Semiconductor industry with a strong focus on Ethernet and high-speed networking technologies, delivering reliable, scalable solutions for performance- and power-critical systems. My work spans the full design lifecycle, from architecture and RTL development through validation and bring-up, balancing throughput, latency, power efficiency, security, and functional safety to meet demanding product requirements. I utilize FPGAs as a prototyping platform and a means to de-risk complex digital designs, enabling rapid iteration, architecture validation, and translation into robust, production-ready solutions.Beyond technical execution, I collaborate with cross-functional teams across multiple sites, including systems, software, security, safety, verification, validation, applications, and physical design teams. I value clear communication and alignment, ensuring complex technical concepts are understood and decisions are made efficiently. I take an active role in project planning and execution to keep programs on schedule and stakeholders informed.I am motivated by solving complex problems at the intersection of networking, performance, and power, and I enjoy contributing both as a hands-on engineer and as a dependable project and technical lead within global teams.

Experience

1. Digital Design Engineer

   Texas Instruments

   Aug 2018 — Present · Dallas-Fort Worth, TX, US

   Member, Group Technical Staff (MGTS)• Led the definition and design of a next-generation networking accelerator for automotive and industrial SoCs (Jacinto, Sitara, ASM), meeting strict power, performance, security, and safety targets.• Drove the end-to-end delivery of TI\'s first dynamic, multi-protocol network offload engine with TI’s first internally developed RISC-V core, achieving >20x improvement in packet throughput (600Kpps →15Mpps).• Managed system-level trade-off decisions for high-speed Ethernet IPs, integrating input from systems, security, and safety teams to deliver Layer 4 routing and TCP/UDP/IP offload capabilities on schedule.• Led the development and execution of additional networking and interface IPs (DDR/LPDDR, SENT, UFS 3.0, CPSW/ALE) for automotive and industrial customers, enabling DRAM performance, new sensor interfaces, higher storage bandwidth, and improved robustness of 10 Gbps Ethernet switching for unicast/multicast traffic.• Performed transient fault injection (Cadence FSV) and formal verification (Cadence JasperGold), achieving safety certification targets for 5+ audited SoCs and reducing verification schedules by ≥10%.• Led Xilinx FPGA-based modeling and emulation for 10+ SoC programs to enable early software development, validate 10Gbps line-rate Ethernet performance at sub-3µs latency, and accelerate architecture decisions.• Defined the networking roadmap from translated customer requirements and market signals, collaborating with global and cross-functional teams to ensure alignment from concept through production.• Demonstrated program ownership by building multi-quarter roadmaps, managing schedules, critical-path dependencies, and risks, and communicating status and technical decisions to senior stakeholders.• Represented TI as a voting member of 802.3.• Mentored 15+ junior engineers and interns, onboarding them in IP design/DV and networking/Ethernet as the go-to networking subject-matter expert.

Education

• Purdue University

  Bachelor of Science (B.S.), Electrical Engineering

  2014 — 2018

• Rice University

  Master of Business Administration - MBA, Business Administration and Management, General

Skills

• Python
• C
• Programming
• Microsoft Office
• Verilog
• Gwt
• Microsoft Excel
• Perl
• Management
• Tl-Verilog
• Customer Service
• Microsoft Word
• Electrical Engineering
• Java
• Matlab