Arjun Nag

About Arjun Nag

Design Verification Engineer in the field of VLSI• Hands on Experience in System Verilog, Verilog & VHDL.• Good Knowledge of UVM (Universal Verification Methodology).• Good understanding of SoC level Test bench Architecture• Good Hands-on at RTL - C Co simulation on HLS tool• Well versed in creating the interface & module level UVC’s• Good understanding of Processor boot flows• Good understanding of Verification flow at SoC level• Good Knowledge of FPGA, ASIC & SoC Design & Verification Life Cycles.• Excellent understanding of protocols like UCIe 1.0, PCIe (Gen 2, 3 & 5), Compression/decompression Engine, QSPI, AMBA AXI, SMB & HTP• Good Knowledge in both functional and gate level simulations.• Possess hands on experience in Emulating complex SoC designs, Interface Build-up and Debugging.• Good understanding of Design Partitioning and Trimming.• Hands-on Working experience of Mentor Veloce Quattro 2 & MAXIMUS Emulators.• Mentor Veloce Quattro 2 based Emulation setup and chip compile/run hands on experience• Experience in Emulating Complex memory controllers and functional IP blocks in In Circuit Emulation (ICE) and TBX Modes.• Good understanding of differences between RTL and X-RTL.• Well versed in setting up software top and hardware top in a Top Level Emulation test bench.• Excellent debugging skills• Excellent Documentation skills• Knowledge of Configuration Management tools like Tele logic DOORS and CM Synergy tools.• Fair Knowledge of IBM rational Tools like Clear Case and Clear Quest• Familiar with concepts of C Language and Object Oriented Methodology.• Possess excellent communication & articulation skills, interpersonal relations, analytical skills, hardworking and result oriented as an individual and in a team.• Willing to learn new skills and ability to learn fast.• Technical support to team membersSpecialties & Highlights : • SystemVerilog, Verilog, VHDL, UVM, FPGA, ASIC, SOC, Active-HDL 8.3,Rivera Pro 2019.10, AMD(Xilinx) Vivado 2025.1,Model Sim 10,Questa Sim12.c,Cadence Xcelium, Synopsys VCS, Rapid Prototyping & Emulation, Hardware Software Co-Verification.• System Verilog UVM/OVM/VMM based SoC / ASIC/ IP Design Verification on assertion based Constrained Random Verification (CRV) with Functional and Code coverage and RTL (Verilog HDL & VHDL) development

Experience

1. Senior Design Verification Lead

   Tata Consultancy Services

   May 2020 — Present · Hyderabad, IN

   Project Name: IP & SoC Verification of QSPI Flash ControllerClient Name : Domestic RISC-V based Processor companyTeam Size: 10Role : Senior Verification LeadLanguage Used : UVMTools : Aldec Riviera Pro 2020.10Project Description : QSPI is an enhanced version of standard SPI which enables single, dual and quad mode which increases the data throughput at higher frequencies. It has been specifically designed for talking to flash chips that support this interface. The main focus in our work was to verify the QSPI module by configuring the available registers, perform write operation to flash and read data back from flash, and perform data integrity. The design of QSPI is done in Blue spec System Verilog (BSV). The Verilog equivalents of QSPI design were generated using the BSV compilers and toolsResponsibilities:• Understanding the complete QSPI protocol.• Generating Verilog equivalents of QSPI design using the BSV compilers and tools• Design & Development of UVM components,Test Sequences, Test cases • Preparation of IP & SoC level Test plan.• Development of various Test cases based on Test plan.• Filing the bugs and informed to Design team.

Education

• Jawaharlal Nehru Technological University

  MTech, Digital Systems & Computer Electronics

  2007 — 2009

• Andhra University

  B.E, Electrical & Electronics

  2002 — 2006

• INSEAD

  Digital Growth & Transformation

• Jawaharlal Nehru Technological University, Anantapur

  Doctor of Philosophy - PhD, Digital IC Design & Verification Methodologies-Re-usable UVM based complex SoC Verification & TTM

Skills

• Soc
• Coverage Analysis
• Analysis
• Static Timing Analysis
• Digital Electronics
• Embedded Systems
• Eda
• Formal Verification
• Electronics
• Rtl Design
• Processors
• Digital Design
• Microcontrollers
• Xilinx
• Systemverilog
• Vlsi
• Jtag
• Rtl Coding
• Logic Design
• Specman
• Integrated Circuit Design
• Microprocessors
• C
• Ahb
• Vcs
• Verilog
• Uvm
• Quartus
• Nc-Verilog
• Hardware Verification
• Modelsim
• Vhdl
• Simulations
• Tcl
• Timing Closure
• Hardware Architecture
• Open Verification Methodology
• Hardware
• Altera
• Simulation