Arjita Rai Jain

About Arjita Rai Jain

Currently working fulltime as a Staff R&D Engineer @ Synopsys in Circuit Design & TCAD Solutions Team which is now Silicon Technology Group.2. Worked as Project Lead @ TechM Cerium to co-ordinate and track a team of engineers. As a Individual contributor currently working on Receiver blocks like CDR, Summer, DFE etc to support PCIe_GEN6 PAM-4 64Gbps & NRZ 32Gbps PHY.3. Worked as Sr. Analog Design Engineer @ TechM Cerium in High Speed D-PHY based MIPI & High Speed IO based TBT, USB, DP, HDMI, PCIE RX architectures using lower technology nodes 14nm, 10nm,7nm FinFETs.4. Block ownership for High Speed clock path, Serial to parallel converters, Level Shifters, Comparators, CDR, DFE, CTLE, squelch etc.Professional Summary:• Design and develop complex mixed signal circuitry supporting High speed SERDES Design, CoreAnalog & General Purpose I/O blocks in various process nodes.• Involved in circuit design updates based on process/performance/age/eos/rv related spec violations.• Working closely with other cross-functional teams for design sign-off.• Define layout constraints and suggest fixes based on simulation & reliability post layout results.• Replicate Post-Silicon findings in Simulation Environment with channel and related components.• Experienced to work in multiple projects with available resources, timelines, and challenges of lower technology node.Programming Languages Known : PERL,TCL,UNIXExposure to following EDA Tools:• Cadence Virtuoso ADE, ADEXL, Maestro, Verifier• Synopsys Custom Compiler, PRIMESIM, HSPICE, FINESIM• ELDO, SPECTRE, LYNX

Experience

1. Staff R & d Engineer

   新思科技股份有限公司

   Mar 2024 — Present · Bengaluru, IN

Education

• Kendriya Vidyalaya

  Class 10, Science

  2006 — 2007

• SHARDA UNIVERSITY

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2009 — 2013

• Banasthali Vidyapith

  Master of Technology (M.Tech.), VLSI DESIGN

  2015 — 2017

• Kendriya Vidyalaya

  Class 12, science

  2008 — 2009