Arindom Sharma
INTEL || Physical Design Timing Engineer
- Role
- Senior Physical Design Timing Engineer at Intel
- Location
- Jorhat, AS, IN
- LinkedIn followers
- 500 followers
Experience
Senior Physical Design Timing Engineer
Feb 2026 — Present
Education
Jorhat Institute of Science & Technology
Bachelor of Engineering (B.E.), electronics and telecommunication
2014 — 2018
Pragjyotika Academy
Higher Secondary, Science
2012 — 2014
Malaviya National Institute of Technology Jaipur
Master of Technology - MTech, VLSI Design
2021 — 2023
Skills
- Microsoft Office
- C++
- C
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