Arijit Banerjee
- Role
- Mts Design Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Arijit Banerjee
Experienced in full custom or semi-custom Energy efficient custom digital and SRAM…
Experience
Mts Design Engineer
Nov 2018 — Present
R&D in SRAM design verification for L2/L3 cores.
Skills
- Synopsys Dve
- Canary Sram Sensor Design for Arbitrary Vmin Guardband Lowering
- Design Rule Checking (Drc)
- Application-Specific Integrated Circuits (Asic)
- Energy Efficient and Low Vmin Sram Design
- Matlab
- Canary Sensor Based Adaptive Dvs Iot Soc Design
- Rtl Design
- Cadence Virtuoso
- Physical Design
- Very-Large-Scale Integration (Vlsi)
- Cadence Soc Encounter
- Ultra Low Power Digital and Memory Circuit Design
- Hspice and Hsim
- Circuit Design
- Io3232
- System on a Chip (Soc)
- Drc
- Lvs
- Synopsys Design Compiler
- Canary Sensor Based Wide Range Iot Adaptive Dvs Systems Design
- Drc, Lvs, Xrc, Dfm
- Sram Design
- Mentor Calibre
- Perl
- Low-Power Design
- Peripheral Assists for Sram
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