Arif Mohammed

About Arif Mohammed

20+ years of experience in ASIC SoC Design Verification. TUV certified FS Engineer(2023) TUV trained TUV-NORD (2016). Led five devices TUV ASIL certification representing design deliverable work products working with Functional Safety manager. DV Lead: 10+ projects. Design Lead: Three SoC designs (low cost 7mm2 to high performance 60+mm2 devices)Current role : SoC Design Lead of ASIL-D device with quad core new CPUs, 60mm2 device.People management: Front End Design Manager: 45+ reports (RTL, DV and AVV domains)• Exposure to verification, functional safety (FMEDA, Fault injection). Handled fault injection for two SoC designs (Assessed and Certified). Created FI strategy, planned safety mechanisms, SM/FM FI sims.• Experience in creating test-benches and \"C test-cases for SoC DV• Experience in creating verification plans for IP/SOC verification.• Working experience in complex SOC verification using ARM(Cortex-M3, ARM-9), DSP, and microcontrollers Handled IP verification at module level(\"Specman/E\" and FV) and SOC level• Experience in GLS• Post-Silicon debug especially on ATE [ TDL Patterns for AC characterisation] and Validation-Debug-Board test-bench support• STA lead• Specification ownership (Two SoC design specs, Two IP specs)• Worked in creating Qualitative FMEDA for a SOC design for IEC-61508 safety certification• People management[ Supervision - 45+ reports]- From 2008 onwardsVHDL, Verilog, System Verilog, Assembly, C, SVA, UVMScripting Languages : Perl and TCLCPU cores: Cortex-M3, M4, ARM-9, TI C6x and C28xProtocols: AMBA(AHB, APB), TI Perilpheral Bus and Processor interconnectsPeripherals: EtherCAT, EMAC, PMBUS, I2C, CAN, SDRAM, DDR, SPI, MCSBP,uPP, USBEDA Tools: Xcelium, JG FV APPS. XFS/FCM (FuSa) DC, PT(STA), LECInternal and External publications/papers/posters: 25+.CadenceLIVE India 2024—Expert Committee MemberSession chair person (Scoring, Judging Best paper in Advanced Verification Group) for CDNLIVE 2017, CDLIVE 2022TIITC DV track co-chair-2020, 2023, Chair-2022Invited as Motivational speaker at Cadence for 2017 Best paper awards - 2 (CDNLive-2016-System verification, TIITC2023-DV track, FuSa paper)Conference details: DAC - 2DVCON -3 (2014,2015, 2016)CDNLIVE AMERICAS - 2 (FuSA related 2021)CDNLIVE INDIA- 4 (2014-2, 2015-1, 2016-1)SNUG-1TI Internal Conferences (TIITC, TLC): 10US Patents Approved: 2TI MIA awards: 2TI COG award: 1

Experience

1. Senior Lead Dv Domain

   Texas Instruments

   Jan 2001 — Present · IN

Education

• St.Anthony's High School

  B.E, Elec & Comm Engg

• Andhra University College of Engg

  B.E, ECE

  1996 — 2000

Skills

• Static Timing Analysis
• Logic Synthesis
• Soc
• Systemverilog
• Debugging
• Functional Verification
• Modelsim
• Ncsim
• Application-Specific Integrated Circuits (Asic)
• Tcl
• Verilog
• Vhdl
• Asic
• Eda