Archit Badhe

About Archit Badhe

Currently, I’m working as a Physical Design Intern at NXP Semiconductors, specializing in Physical verification (DRC, LVS, MRC, Antenna checks), pad ring design, bump placement for ESD protection, and. I optimize layouts and GDS for manufacturability and reliability, with experience in TSMC 16nm and 5nm technologies. Languages: Verilog, TCL scripting, Python, C Hands on experience on industry-standard tools: Cadence Virtuoso, Mentor CALIBRE, Synopsys Fusion Compiler, Modelsim, Intel Quartus Prime, ICC2, DC shell, Prime time(Synopsys), VIPER. Core Skills: Physical Design, Physical Verification, Digital Design. Proficient in VLSI fundamentals, including digital electronics, CMOS technology, Digital IC Design, Verilog, and TCL scripting. Technolgies worked on - TSMC 16nm and 5nm

Experience

1. Physical Design Intern

   NXP Semiconductors

   Aug 2024 — Present · Bengaluru, IN

   Block-Level SOC Layout Verification: Performed DRC, LVS, MRC and antenna checks and fixes for Top (SOC) level as well as block level. Identified and resolved DRC violations.• Responsible for Physical Verification Signoff for SOC level and sub-system partitions• Worked on TSMC 16nm technology and developed my skills by learning and implementing it in my work during the TAPEOUT.• Created pin-draft and pin-placement draft for the initial floorplan phase.• Currently working on TSMC 5nm Technology project • Scripting Languages: Developed and maintained scripts using Python and TCL to automate various tasks and improve workflow efficiency.

Education

• Model college of science and commerce

  Hsc

• Vivekanand Education Society's Institute Of Technology

  Bachelor of Engineering - BE

  2017 — 2021

• Vellore Institute of Technology

  Master of Technology - MTech in VLSI Design

  2023 — 2025