Archit Shrivastava

About Archit Shrivastava

Extensive experience in design implementation from Netlist to GDS.Implementation experience with Multiple nodes 4nm/5nm being the latest, started from 28nm, experience with multiple foundries Samsung/TSMC/Intel.Have been part of 20+ tapeouts.Vast experience in implementation consisting Floorplanning, Placement, CTS, Routing (Synopsys ICC & ICC2, Cadence Innovus)Expertise in handling Custom CTS planning. Multipoint CTS implementation along with handling Multiple clocks- Blocks with sub-system (hierarchical block and hierarchical top implementation)- Block with Multiple Power domain- Having understanding of DRC, LVS- Extraction (STAR-RC)- Block Level STA (PT-PTSI/Tempus)- Top Level STA (Interface Timing Closure)- Complex ECOs implementation (High Frequency implementation, Latch based designs)- Scripting:(TCL)- Synthesis (DCT) short term exposure, during initial years- Formal Verification (Formality). Have experience in debuging Formal issues- Managing the team, in multiple Project, mainly overseeing the closure of the block.

Experience

1. Senior Staff Engineer

   Qualcomm

   Dec 2025 — Present · Bengaluru, IN

Education

• Truba Institute of Engineering & Information Technology, Karod-Gandhi Nagar By-Pass Road, Bhopal-462036

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

  2006 — 2010

Skills

• Icc2
• Tcl
• Floorplanning
• Design Rule Checking (Drc)
• Icc
• C
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Lvs
• Logic Synthesis
• Physical Design
• Synopsys Primetime
• Soc
• Semiconductors
• Static Timing Analysis
• Synopsys Tools
• Timing Closure
• Asic
• Drc
• Formal Verification
• Vlsi