Archana Shenoy
- Role
- Soc Design Engineer at 英特尔
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
About Archana Shenoy
Electrical engineering masters student in VLSI and mixed signal circuit design at Arizona…
Experience
Soc Design Engineer
Jun 2017 — Present · Santa Clara, CA, US
Working on IP integration and front-end validation using system Verilog test bench as a part of a central team that aims to reduce IP integration time and complexity at SoCs
Education
Arizona State University
Master’s Degree, Electrical Engineering - VLSI and Mixed signal circuit design
2015 — 2017
National Institute of Technology Karnataka
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2008 — 2012
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