Archana Ch
ASIC Verification Engineer at Excel Max
- Role
- Senior Design Verification Engineer at Excelmax Technologies
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Archana Ch
Strong Digital and Logic Design knowledge.Good knowledge on the Verilog.Experience in System Verilog,UVM MethodologyFamiliar knowledge in writing System Verilog assertions.Very good debugging skillsFamiliar knowledge of C language,Perl,Matlab.Experience in the constraint random and coverage driven features in verification environment.Basic knowledge on 802.3 format Ethernet.Strong Digital and Logic Design knowledge.Good knowledge on the Verilog.Experience in System Verilog,UVM MethodologyFamiliar knowledge in writing System Verilog assertions.Very good debugging skillsFamiliar knowledge of C language,Perl,Matlab.Experience in the constraint random and coverage driven features in verification environment.Good knowledge on AMBA protocols and 802.3 format Ethernet.
Experience
Senior Design Verification Engineer
Jun 2023 — Present · Bengaluru, IN
Education
Zph School
Diploma
2011 — 2014
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