Aravind Motamarri

DFT Engineer | ASIC at NVIDIA

Role
Sr Dft Engineer at NVIDIA
Location
Santa Clara, CA, US
LinkedIn followers
500 followers

About Aravind Motamarri

Currently working at Nvidia as DFT engineer, I completed Masters at the University of Cincinnati, with professional experience in the VLSI testing field. I am greatly looking forward to challenging and responsible positions with a strong motive to excel in VLSI physical design, CAD(design automation), VLSI Design for Testing and Low Power. As an electrical major(specialization in VLSI), I\'m fascinated by the upcoming miniaturization of Industrial chips and expansion in their functionality.Highly motivated, organized and hardworking student with excellent presentation and leadership skills, with experience in leading technical and non-technical teams.Technology Proficiency I’m an active learner and I have the acumen to analyze details with critical reasoning. My technology proficiency includes:• Programming Languages: Verilog, VHDL, C, C++, LabVIEW, MATLAB, Python, SAS, SQL, MySQL.• Layout editor Tools: Magic.• EDA Tools: Synopsis IC compiler, Design Compiler (Power Compiler, DFT Compile, and BSD compiler), Tetramax ATPG, Smartest.• Simulation Tools: SPICE, IRSIM, Multisim, MPLAB IDE, ModelSim, Labview, Matlab, Simulink. • Operating Systems: Linux/Ubuntu, WindowsI’ve worked hard to earn accolades from colleagues and contribute to the organization’s growth My colleagues know me as a versatile, well-organized, hard-working problem solver who understands the quality of deliverable and is flexible to adapt new situations. Recognized for my proactive nature and bounteousness, I’ve established myself as a strong team player as well as a leader. I believe knowledge is augmented through teamwork.

Experience

  1. Sr Dft Engineer

    NVIDIA

    Apr 2017 — Present · San Francisco, CA, US

    Implement, verify and enhance test vehicle DFT and DFx logic, includes being involved in all details of ATE test strategy.• Improve test structure and test patterns for better defect isolation and characterization.• Implement and improve a variety of automation scripts used to implement test vehicle and isolate failures.• Interact with internal cross-functional groups to determine and fulfill design automation needs.• lead the root cause of process and design issues using state of the art onsite EFA lab.

Education

  • University of Cincinnati

    Master’s Degree, Electrical Engineering (Specialization in VLSI)

    2015 — 2017

  • Amrita School of Engineering

    Bachelor’s Degree, Electronics and Instrumentation

    2010 — 2014

  • Sri Chaitanya Junior College

    High School, Mathematics Physics and Chemistry

    2008 — 2010

Skills

  • Debugging
  • Unix
  • Verilog
  • Application-Specific Integrated Circuits (Asic)
  • Semiconductors
  • Physical Design
  • Databases
  • Labview
  • Mysql
  • Smartest
  • Integrated Circuit Design
  • Perl
  • Embedded Systems
  • Eda
  • Linux
  • Modelsim
  • Simulink
  • Vlsi Testing
  • C
  • Programming
  • Python
  • Vlsi Automation
  • System on a Chip (Soc)
  • Testing
  • Spice
  • Windows
  • Electronics
  • Microsoft Office
  • Vlsi
  • Vhdl
  • Simulations
  • C++
  • Operating Systems
  • Powerpoint
  • Microsoft Excel
  • Dft
  • Matlab

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