Aravindan Seshadri
- Role
- Senior Design Verification Engineer at NVIDIA
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Aravindan Seshadri
ASIC/Digital design verification professional SKILL SUMMARY: Design & …
Experience
Senior Design Verification Engineer
Mar 2022 — Present
Skills
- Customer Service
- Very-Large-Scale Integration (Vlsi)
- Vhdl
- Drc
- Perl
- Cadence Spectre
- Cadence Encounter
- Application-Specific Integrated Circuits (Asic)
- Vlsi
- Perl Script
- Spectre
- Verilog
- Synopsys Tools
- Synopsys Primetime
- Physical Design
- Asic
- Modelsim
- Electronics
- C
- Rtl Verification
- Analog Circuit Design
- I2c
- Tcl
- Digital Signal Processors
- Lvs
- Cadence Virtuoso
- Uvm
- Systemverilog
- Awr Microwave Office
- System Verilog Assertion
- Tetramax
- Integrated Circuit Design
- Open Verification Methodology
- Cmos
- Synopsis
- Primetime
- Cadence Virtuoso Layout Editor
- Simulations
- Pcie
- Xilinx Ise
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