Aravind Sundararaj
- Role
- Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Aravind Sundararaj
Multiple Tape-outs from 180nm to 3nm technology
Experience
Present
Skills
- Embedded Systems
- Vhdl
- Verilog
- Drc
- Primetime
- Low-Power Design
- Magma
- Physical Design
- Low Power Design
- Soc
- Power Analysis
- Place & Route
- C
- Static Timing Analysis
- Semiconductors
- Timing
- Floorplanning
- Logic Synthesis
- Lvs
- Functional Verification
- Eda
- Asic
- Timing Closure
- Physical Verification
- Systemverilog
- Signal Integrity
- Vlsi
- Clock Tree Synthesis
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