Aravind Selvaraj

About Aravind Selvaraj

An enthusiastic verification engineer working on cutting-edge technology in the semiconductor field.Skills : IP and SoC verification FPGA Verification DV Plan creation, execution and end to end DV closure UVM + SystemVerilog Testbench environment bring up from scratch Vplan Mapping and regression development and execution Code and Functional coverage analysis and closure Software-based sample-accurate Reference Model development Complex timing checker design and development Protocols : AMBA APB, AXI3 and AXI4, WiFi 802.11ax, Massive MIMOResponsibilities Held : eFuse memory controller technology DV Security subsystem verification - ROT Processor DV SW BOOT Code verification Image Processor Subsystem - IP and SoC DV DSP Core, DSP SoC level verification Block/Subsystem/SoC level Verification of 5G Wireless systems Clocking, synchronization and coverage driven DV Real-time software modeling with SystemC/SystemVerilog against RTL for sample check.

Experience

1. Asic Design Verification Engineer

   Google

   Jun 2022 — Present · Bengaluru, IN

   Bare metal security manager core IP DV Lead eFuse memory controller DV LeadSecure manufacturing process verification RoT processor BOOT code verification

Education

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Electrical, Electronics and Communications Engineering

  2019 — 2021

• PSG College of Technology

  Bachelor of Engineering (B.E.), Electronics and Communication

  2013 — 2017

Skills

• Embedded Systems
• Analog Circuit Design
• C
• Programming
• Management
• C++
• Project Management
• Systemverilog
• Functional Verification
• Software Development
• Snooker
• Shell Scripting
• Matlab
• Microsoft Office
• Vlsi
• Linux
• Integration